Using early integrated circuit (IC) fabrication techniques, integrating both bipolar and MOS transistors into a single IC device was difficult and uneconomical. For this reason, depending upon the function to be performed, most early ICs included either bipolar transistors fabricated using a bipolar process flow, or MOS transistors fabricated using, for example, a complementary metal-oxide-semiconductor (CMOS) process flow. CMOS is currently the dominant IC fabrication technology for most common types of ICs.
Integrated bipolar and complementary metal-oxide-semiconductor (BiCMOS) fabrication techniques were introduced in the late 1990s to facilitate the efficient production of IC devices that include both bipolar and MOS transistors formed on the same semiconductor substrate. The advantage of BiCMOS devices is that they combine the high power and fast switching speeds of bipolar devices with the high density and low power consumption of MOS transistors, which provides the advantages of noise immunity, linearity, device matching, and high drive capacity, thus permitting performance optimization and a higher degree of system integration. A disadvantage of BiCMOS devices is that, because BiCMOS is not as well developed as CMOS and bipolar techniques, BiCMOS feature sizes are generally larger than those achievable using CMOS and bipolar fabrication techniques, and individual device performance is typically slower.
Like bipolar and CMOS fabrication techniques, BiCMOS process flows include hundreds of complex and mutually interdependent processing steps that must be performed in a well-defined sequence in order to build BiCMOS circuits successfully. These steps, as well as their sequence, must be carefully planned to assure high yield, adequate performance, and acceptable cost.
Some IC designs require the inclusion of non-conforming circuit structures (i.e., circuit structures that cannot be produced using the established process flow). When this occurs, it is necessary to add masks and/or process steps to the existing process flow, which at a minimum increases processing time and cost, and in the worst case requires substantial “tweaking” of the modified process flow in order to produce acceptable yields.
As example of a possible non-conforming circuit structure is a non-volatile memory cell. Non-volatile memory (e.g., Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and flash memory), unlike volatile memory (e.g., read-only memory (RAM)), is capable of preserving information without a power supply. The information is preserved on a floating gate (i.e., a doped polycrystalline silicon structure that is entirely surrounded by insulation), and floating gate is erased (i.e., charged added to or drawn from) or programmed (i.e., drawn from or added to) by creating a suitable potential between the floating gate and an adjacent conductor that is high enough to cause injection or tunneling of electrons through the insulation layer. Because non-volatile memory is able to retain data when power is lost, demand for non-volatile memory has increased along with the rise in usage of battery-powered portable electronic devices, such as cellular phones, MP3 players, and digital cameras.
In the field of non-volatile memories there is an advantage to isolate the P-body of an N-channel Flash cell. The advantage provided by isolating the P-body is that this isolation reduces the level of voltage required to pump from the standard supply voltages to achieve a minimum electric field of 10 Mv/cm, which is the minimum required to produce the onset of Fowler-Nordheim tunneling. By having an isolated P-body one can bias the P-body and the control gate to achieve 10 Mv/cm across the body and floating-gate, thereby reducing the burden of the charge pump. For example, one could bias the control-gate to −6V and the P-body to 6V to achieve 12 MV/cm on a 100 Angstrom gate oxide (assuming a coupling ratio of one). In contrast, when the body is not isolated, one would need to pump the voltage to −12 V on the control-gate or 12V on the source, which creates the further burden of providing a high voltage source.
Traditionally, an isolated P-body is accomplished by a complicated triple well process that is not part of a standard CMOS process flow. Because triple-wells cannot be formed by typical CMOS process flows, the selected CMOS flow must be modified to include additional masks and processing steps, which increases overall production costs and typically reduces production yields.
Similar to CMOS process flows, non-volatile memory cells are considered non-conforming in conventional BiCMOS process flows.
What is needed is a non-volatile memory cell and method for forming such a cell using a BiCMOS process flow in a manner that minimizes the number of additional masks and/or process steps.